SAN FRANCISCO–While the transistor may be on the minds of many a process R&D engineer these days, back-end-of-line (BEOL) interconnect technology and the materials challenges there– namely integrating ...

Stacking chiplets vertically using short and direct wafer-to-wafer bonds can reduce signal delay to negligible levels, enabling smaller, thinner packages with faster memory/processor speeds and lower ...

Asymmetries in wafer map defects are usually treated as random production hardware defects. For example, asymmetric wafer defects can be caused by particles inadvertently deposited on a wafer during ...

The Soitec Group and the SEZ Group have initiated a joint development program (JDP) intended to speed the industrialisation of next-generation strained silicon-on-insulator (sSOI) substrates. Under ...

Power consumption is a crucial consideration for all types of electronics. As critical power components used in a wide range of electronic products, power MOSFET and other types of power semiconductor ...

It uses two wafers instead of one, along with ultra-thin dielectric bonding ...

Imec and Sony have developed a novel integration module for highly dense backside interconnects – key components of 3D stacking and backside functionalisation technologies. The module is structured ...