Design And Reuse

MIPS accelerates the development timeline of the RISC-V NPU S8200, integrating Synopsys ARC IP to transform into a "physical AI" computing platform.

A veteran processor architect striving to regain its glory in the RISC-V architecture arena.MIPSMIPS has been making frequent moves recently. It announced that it will accelerate its designs for edge ...
DIGITIMES

MIPS accelerates S8200 RISC-V NPU timeline

MIPS has accelerated the development timeline of its S8200 neural processing unit, a RISC-V–based NPU designed for real-time, ...